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| HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RAM ADE-203-280A (Z) Rev. 1.0 Dec. 20, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance. Features * * * * * * * * 3.3V Power supply Clock frequency: 100 MHz/83 MHz/66 MHz LVTTL interface Single pulsed RAS 2 Banks can operates simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Programmable CAS latency: 1/2/3 Byte control by DQMU and DQML Refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh * * * * HM5216165 Series Ordering Information Type No. HM5216165TT-10H HM5216165TT-10 HM5216165TT-12 HM5216165TT-15 Frequency 100 MHz 100 MHz 83 MHz 66 MHz Package 400-mil 50-pin plasticTSOP II (TTP-50D) Pin Arrangement HM5216165TT Series VCC I/O0 I/O1 VSSQ I/O2 I/O3 VCCQ I/O4 I/O5 VSSQ I/O6 I/O7 VCCQ DQML WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (Top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O15 I/O14 VSSQ I/O13 I/O12 VCCQ I/O11 I/O10 VSSQ I/O9 I/O8 VCCQ NC DQMU CLK CKE NC A9 A8 A7 A6 A5 A4 VSS 2 HM5216165 Series Pin Description Pin name A0 to A11 Function Address input Row address Column address I/O0 to I/O15 CS RAS CAS WE DQMU DQML CLK CKE VCC VSS VCCQ VSS Q NC Data-input/output Chip select Row address strobe command Column address strobe command Write enable command Upper byte input/output mask Lower byte input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for I/O pin Ground for I/O pin No connection A0 to A10 A0 to A7 A11 Bank select address 3 HM5216165 Series Block Diagram A0 - A11 A0 - A7 A0 - A11 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Sense amplifier & I/O bus Memory array Column decoder Sense amplifier & I/O bus Memory array Column decoder Bank 0 2048 row X 256 column X 16 bit Bank 1 2048 row X 256 column X 16 bit Input buffer Output buffer Control logic & timing generator I/O0 - I/O15 DQMU DQML CKE RAS CAS CLK WE CS 4 HM5216165 Series Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged. A11 (input pin): A11 is a bank select signal (BS). The memory array of the HM5216165 is divided into bank 0 and bank 1, both which contain 2048 row x 256 column x 16 bits. If A11 is Low, bank 0 is selected, and if A11 is High, bank 1 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output buffers. Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQMUL is Low, the output buffer becomes Low-Z. Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If DQMU/DQML is Low, the data is written. I/O0 to I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a conventional DRAM. VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer). VSS and V SS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) 5 HM5216165 Series Command Operation Command Truth Table The synchronous DRAM recognizes the following commands sepcified by the CS, RAS, CAS, WE and address pins. Function Ignore command No operation Burst stop in full page Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank act. Precharge select bank Precharge all bank Refresh Mode register set Symbol DESL NOP BST READ READ A WRIT WRIT A ACTV PRE PALL CKE n-1 n H H H H H H H H H H x x x x x x x x x x V x CS H L L L L L L L L L L L RAS CAS WE x H H H H H H L L L L L x H H L L L L H H H L L x H L H H L L H L L H L A0 A11 A10 to A9 x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V REF/SELF H MRS H Note: H: VIH. L: VIL. x: V IH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256)), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data (256), it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page (256), this command is illegal. 6 HM5216165 Series Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A11) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7) and the bank select address (A11). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page (256), this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11 (BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is High, bank 1 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh oepration, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. DQM Truth Table CKE n-1 H H H H Function Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte write inhibit/output disable Note: H: VIH. L: VIL. x: V IH or VIL. I DOD is needed. Symbol ENBU ENBL MASKU MASKL n x x x x DQMU L x H x DQML x L x H The HM5216165 series can mask input/output data by means of DQMU and DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5216165 operating instructions. 7 HM5216165 Series CKE Truth Table CKE n-1 H L L REF SELF H H H H Self-refres Self refresh exit SELFX L L Power down Power down exit L L Note: H: VIH. L: VIL. x: V IH or VIL. CS H x x L L L H L H L H RAS x x x L L H x H x H x CAS x x x L L H x H x H x WE x x x H H H x H x H x Current state Active Any Clock suspend Idle Idle Idle Function Clock suspend mode entry Clock suspend Clock suspend mode exit Auto refresh command Self refresh entry Power down entry n L L H H L L L H H H H Address x x x x x x x x x x x Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAMs.) During the auto refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto refresh, no precharge command is required after auto refresh. 8 HM5216165 Series Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self refresh operation. After the execution of this command, self refresh continues while CKE is Low. Since self refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE state. Power down exit: When this command is executed at the power down mode, the synchronous DRAM can exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE state. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state Precharge CS H L L L L L L L L Idle H L L L L L L L L RAS CAS WE x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL ILLEGAL ILLEGAL NOP ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL ILLEGAL Bank and row active NOP Refresh Mode register set 9 HM5216165 Series Current state Row active CS H L L L L L L L L Read H L L L L L L L L Read with auto-precharge H L L L L L L L L RAS CAS WE x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop on full page Continue burst read to CAS latency and new read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL 10 HM5216165 Series Current state Write CS H L L L L L L L L Write with auto-precharge H L L L L L L L L Refresh (auto refresh) H L L L L L L L L RAS CAS WE x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and new read Term burst and new write Other bank active ILLEGAL on same bank*3 Term burst write and precharge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes: 1. H: VIH. L: VIL. x: V IH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. 11 HM5216165 Series From [PRECHARGE] To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of precharge. From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read oepration starts. (However, an interval of tRCD is requried.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of t RAS is required.) From [READ] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is requried.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode. 12 HM5216165 Series From [READ with AUTO PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From [WRITE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode. From [WRITE with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the synchronous DRAM automatically enters the IDLE state. 13 HM5216165 Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MODE REGISTER SET MRS IDLE REFRESH *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE CLOCK SUSPEND ACTIVE CKE_ CKE ROW ACTIVE BST (on full page) BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE CKE WRITE WITH AP CKE_ WRITEA SUSPEND WRITEA CKE PRECHARGE READ WITH AP WRITE WITH AP READ READ WITH AP WRITE READ Read CKE_ READ CKE READ WITH AP CKE_ READA CKE PRECHARGE READA SUSPEND READ SUSPEND WRITE WITH AP PRECHARGE POWER APPLIED POWER ON PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 14 HM5216165 Series Mode Register Configuration The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A11, A10, A9, A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length. A11 A10 A9 A8 A7 0 A6 A5 A4 A3 BT A2 A1 BL A0 OPCODE LMODE A6 0 0 0 0 1 A5 0 0 1 1 X A4 CAS Latency 0 1 0 1 X R 1 2 3 R A3 Burst Type 0 Sequential 1 Interleave A2 A1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length BT=0 1 2 4 8 R R R F.P. BT=1 1 2 4 8 R R R R A11 0 X X X A10 0 X X X A9 0 0 1 1 A8 0 1 0 1 Write mode Burst read and burst write R Burst read and SINGLE WRITE R F.P. =Full Page (256) R is Reserved(inhibit) X: 0 or 1 15 HM5216165 Series Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, 16 HM5216165 Series Operation of HM5216165 Series Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank active command cycle. An interval of tRCD is requried between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency-1) cycle after read command set. HM5216165 series can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (256). The start address for a burst read is specified by the column address (AY0 to AY7) and the bank select address (A11) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 1, 2, 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (256), data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register. CAS Latency CLK t RCD Command ACTV READ Address Row Column CL = 1 Dout CL = 2 CL = 3 out 0 out 1 out 0 out 2 out 1 out 0 out 3 out 2 out 1 out 3 out 2 out 3 CL: CAS Latency Burst Length = 4 17 HM5216165 Series Burst Length CLK t RCD Command Address ACTV READ Row Column BL = 1 BL = 2 out 0 out 0 out 1 Dout out 0 out 1 out 2 out 3 BL = 4 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 BL = 8 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 255 out 0 out 1 BL = full page (256) BL: Burst Length CAS Latency = 2 Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the mode register. Burst write A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7) and the bank select address (A11) at the write command set cycle. CLK t RCD Command Address ACTV WRIT Row Column BL = 1 BL = 2 in 0 in 0 in 1 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 in 3 in 4 in 4 in 5 in 5 in 6 in 6 in 7 in 7 in 8 in 255 Din in 0 BL = 4 in 0 BL = 8 in 0 in 0 in 1 BL = full page (256) CAS Latency = 1, 2, 3 18 HM5216165 Series Single write A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is olny written to the column address (AY0 to AY7) and the bank select address (A11) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0). CLK t RCD Command ACTV WRIT Address Din Row Column in 0 CAS Latency = 1, 2, 3 Burst Length = 1, 2, 4, 8 full page 19 HM5216165 Series Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command. CAS latency 3 2 1 Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output same cycle as the final data is output CLK CL = 1 Command Dout READ ACTV out0 out1 out2 out3 lAPR CL = 2 Command Dout READ ACTV out0 out1 out2 out3 lAPR CL = 3 Command Dout READ ACTV out0 out1 out2 out3 lAPR Note: Internal auto-precharge starts at the timing indicated by " ". At CLK = 50 MHz ( lAPR changes depending on the operating frequency. ) 20 HM5216165 Series Write with auto precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is requried between the final valid data input and input of the next command. Burst Write (Burst Length = 4) CLK Command WRIT ACTV I/O (input) in0 in1 in2 in3 lAPW Single Write CLK Command WRIT ACTV I/O (input) in lAPW Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8. CAS latency 1 2 3 BST to valid data 0 1 2 BST to high impedance 1 2 3 21 HM5216165 Series CAS Latency = 1, Burst Length = full page CLK Command I/O (output) out out out out BST out l BSR 0 cycle l BSH 1 cycle CAS Latency = 2, Burst Length = full page CLK Command I/O (output) out out out out BST out out l BSH = 2 cycle l BSR = 1 cycle CAS Latency = 3, Burst Length = full page CLK Command BST I/O (output) out out out out out out out l BSR = 2 cycle l BSH = 3 cycle 22 HM5216165 Series Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is requried between the BST command and the next precharge command. Burst Length = full page CLK Command I/O (input) in in t DPL I BSW = 0 cycle BST PRE/PALL 23 HM5216165 Series Command Intervals Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) CLK Command Address (A0-A10) BS (A11) READ ACTV READ Row Column A Column B Dout Bank0 Active out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout CAS Latency = 3 Burst Length = 4 Bank0 Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank) CLK Command Address (A0-A10) BS (A11) ACTV ACTV READ READ Row 0 Row 1 Column A Column B Dout Bank0 Active Bank1 Bank0 Bank1 Active Read Read out A0 out B0 out B1 out B2 out B3 Bank0 Bank1 Dout Dout CAS Latency = 3 Burst Length = 4 24 HM5216165 Series Write command to Write command interval: Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE toWRITE Command Interval (same ROW address in same bank) CLK Command Address (A0-A10) BS (A11) Din Bank0 Active in A0 in B0 in B1 in B2 in B3 ACTV WRIT WRIT Row Column A Column B Column =A Column =B Write Write Burst Write Mode Burst Length = 4 Bank0 Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank) CLK Command Address (A0-A10) BS (A11) ACTV ACTV WRIT WRIT Row 0 Row 1 Column A Column B Din Bank0 Active in A0 in B0 in B1 in B2 in B3 Bank1 Bank0 Bank1 Active Write Write Burst Write Mode Burst Length = 4 25 HM5216165 Series Read command to Write command interval: Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) CLK Command CL=1 DQMU /DQML READ WRIT CL=2 CL=3 Din in B0 High-Z in B1 in B2 in B3 Dout Burst Length = 4 Burst write READ to WRITE Command Interval (2) CLK Command READ WRIT DQMU /DQML CL=1 2 clock High-Z High-Z High-Z Dout CL=2 CL=3 Din Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. 26 HM5216165 Series Write command to Read command interval: Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1) CLK Command WRIT READ DQMU/DQML Din Dout in A0 out B0 Column=A Write CAS Latency Column=B Read Column=B Dout out B1 out B2 out B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0 WRITE to READ Command Interval (2) CLK Command WRIT READ DQMU/DQML Din Dout in A0 in A1 out B0 Column=A Write CAS Latency Column=B Read Column=B Dout out B1 out B2 out B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0 Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address). 27 HM5216165 Series Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by l HZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by l EP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 1, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 out A1 out A2 out A3 CL=1 l EP = 0 cycle CAS Latency = 2, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 out A1 out A2 out A3 CL=2 l EP = -1 cycle CAS Latency = 3, Burst Length = 4 CLK Command READ PRE/PALL Dout out A0 out A1 out A2 out A3 CL=3 l EP = -2 cycle 28 HM5216165 Series READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 1, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL High-Z Dout out A0 l HZP =1 CAS Latency = 2, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL High-Z Dout out A0 l HZP =2 CAS Latench = 3, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL High-Z Dout out A0 l HZP =3 29 HM5216165 Series Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is unfinished, the input data must be masked by means of DQMU and DQML for assurance of the cycle defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) CLK Command WRIT PRE/PALL DQM Din t DPL CLK Command WRIT PRE/PALL DQM Din in A0 in A1 t DPL Burst Length = 4 (To write all data) CLK Command WRIT PRE/PALL DQM Din in A0 in A1 in A2 in A3 t DPL 30 HM5216165 Series Bank active command interval: Same bank: The interval between the two bank-active commands must be no less than tRC. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank active to bank active for same bank CLK Command ACTV ACTV Address (A0-A10) BS (A11) ROW ROW t RC Bank 0 Active Bank 0 Active Bank active to bank active for different bank CLK ACTV ACTV Command Address (A0-A10) ROW:0 ROW:1 BS (A11) t RRD Bank 0 Active Bank 1 Active 31 HM5216165 Series Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA . CLK Command MRS ACTV Address (A0-A11) CODE BS & ROW t RSA Mode Register Set Bank Active 32 HM5216165 Series DQM Control The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMU/DQML during reading is 2. CLK DQMU /DQML I/O (output) High-Z out 0 out 1 out 3 lDOD = 2 Latency Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0. CLK DQMU /DQML I/O (input) , in 0 in 1 in 3 l DID = 0 Latency 33 HM5216165 Series Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not requried. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not requried. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 s interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Power-down mode: The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table". Power-up sequence: During power-up sequence, the DQMU/DQML and the CKE must be set to High. When 200 s has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register. 34 HM5216165 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1 Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC, VCCQ VSS , VSS Q Input high voltage Input low voltage VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1 Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns 35 HM5216165 Series DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5216165 -10H/-10 Parameter Operating current Symbol I CC1 I CC2 -12 -15 Notes 1, 2, 4 Min Max Min Max Min Max Unit Test conditions -- 130 -- 105 -- 85 mA Burst length = 1 t RC = min Standby current (Bank Disable) -- -- 3 2 -- -- 3 2 -- -- 3 2 mA CKE = VIL, t CK = min 5 mA CKE = VIL CLK = VIL or VIH Fixed mA CKE = VIH, NOP command t CK = min 6 -- 50 -- 41 -- 33 3 Active standby current (Bank active) I CC3 -- -- 7 51 -- -- 7 43 -- -- 7 34 mA CKE = VIL, t CK = min, 1, 2 I/O = High-Z mA CKE = VIH, NOP command t CK = min, I/O = High-Z mA t CK = min, BL = 4 mA 1, 2, 3 Burst operating current (CAS Latency = 1) (CAS Latency = 2) (CAS Latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage I CC4 I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL -- -- -- -- -- 65 -- 55 85 -- -- 45 65 1, 2, 4 100 -- 150 -- 85 2 -- -- 125 -- 70 2 -- -- 100 mA 60 2 mA t RC = min mA VIH VCC - 0.2 VIL 0.2 V A A V V 0 Vin VCC 0 Vout VCC I/O = disable I OH = -2 mA I OL = 2 mA 7 -10 10 -10 10 2.4 -- -- 0.4 -10 10 -10 10 2.4 -- -- 0.4 -10 10 -10 10 2.4 -- -- 0.4 Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode, CLK operating current. 6. After power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 36 HM5216165 Series Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V 0.3 V) Parameter Input capacitance (Address) Input capacitance (Signals) Output capacitance (I/O) Symbol CI1 CI2 CO Min 2 2 4 Max 5 5 7 Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5216165 -10H/-10 Parameter System clock cycle time (CAS Latency = 1) (CAS Latency = 2) (CAS Latency = 3) CLK high pulse width CLK low pulse width Access time from CLK (CAS Latency = 1) (CAS Latency = 2) (-10H) (CAS Latency = 2) (-10) (CAS Latency = 3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance (CAS Latency = 1) (CAS Latency = 2, 3) Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Symbol t CK t CK t CK t CKH t CKL t AC t AC t AC t AC t OH t LZ t HZ t HZ t DS t DH t AS t AH t CES t CESP t CEH Min Max 30 15 10 3 3 -- -- -- -- 3 0 -- -- 2 1 2 1 2 2 1 -- -- -- -- -- 27 9.0 9.5 7.5 -- -- 13 7 -- -- -- -- -- -- -- -12 Min Max 36 18 12 4 4 -- -- -- -- 3 0 -- -- 3 1 3 1 3 3 1 -- -- -- -- -- 32 12 12 9 -- -- 15 9 -- -- -- -- -- -- -- -15 Min Max 45 -- Unit Notes ns 1 22.5 -- 15 5 5 -- -- -- -- 3 0 -- -- 3 1 3 1 3 3 1 -- -- -- 36 17 17 12 -- -- 17 11 -- -- -- -- -- -- -- ns ns ns ns ns ns ns 1 1 1 1 1, 5 1 1 ns ns ns 1, 2 1, 2, 3 1, 4 ns ns ns 1 1 1, 2 37 HM5216165 Series AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (cont) HM5216165 -10H/-10 Parameter Symbol Min Max 2 1 90 60 -- 30 30 15 20 1 -- -- -- -- -12 Min Max 3 1 -- -- -15 Min Max 3 1 -- -- Unit Notes ns ns ns 1 1 1 1 1 1 1 1 1 Command (CS, RAS, CAS, WE, DQM) t CS setup time Command (CS, RAS, CAS, WE, DQM) t CH hold time Ref/Active to Ref/Active command period Active to precharge command period t RC t RAS 100 -- 135 -- 120000 70 120000 -- -- -- -- -- 5 64 30 30 15 20 1 -- 120000 90 120000 -- -- -- -- -- 5 64 45 45 120000 ns 120000 ns -- -- ns ns ns ns ns ms Active to precharge on full page mode t RASC Active command to column command (same bank) Precharge to active command period t RCD t RP Write recovery or data-in to precharge t DPL lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5. t RRD tT t REF 22.5 -- 30 1 -- -- 5 64 AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CKE rising edge except power down exit command. Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures 2.8 V 500 +1.4 V CL t input V SS 80% 20% I/O T tT 38 HM5216165 Series Relationship Between Frequency and Minimum Latency HM5216165 Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) -10H/-10 100 66 Symbol 10 15 t RCD 3 9 6 3 2 2 2 5 9 3 -- -- 1 2 6 4 2 1 2 2 3 6 3 2 -- 1 33 30 1 3 2 1 1 1 2 2 3 3 2 1 1 -12 83 12 3 9 6 3 2 2 2 5 9 3 -- -- 1 55 18 2 6 4 2 1 2 2 3 6 3 2 -- 1 28 36 1 3 2 1 1 1 2 2 3 3 2 1 1 -15 66 15 3 9 6 3 2 2 2 5 9 3 -- -- 1 44 22 22.5 45 2 6 4 2 1 2 2 3 6 3 2 -- 1 1 3 2 1 1 1 2 2 3 3 2 1 1 Notes 1 = [tRAS + tRP] 1 1 1 1 1 2 = [tDPL + tRP] = [tRC] Active command to active command t RC (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) t RAS t RP t DPL Active command to active command t RRD (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable I SREX I APW I SEC I HZP I HZP I HZP I APR I EP I EP I EP I CCD I WCD I DID I DOD I CLE -2 -- -- 1 0 0 2 1 -2 -1 -- 1 0 0 2 1 -2 -1 0 1 0 0 2 1 -2 -- -- 1 0 0 2 1 -2 -1 -- 1 0 0 2 1 -2 -1 0 1 0 0 2 1 -2 -- -- 1 0 0 2 1 -2 -1 -- 1 0 0 2 1 -2 -1 0 1 0 0 2 1 39 HM5216165 Series Relationship Between Frequency and Minimum Latency (cont) HM5216165 Parameter Frequency (MHz) tCK (ns) Register set to active command CS to command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) -10H/-10 100 66 Symbol 10 15 t RSA I CDD I PEC I BSR I BSR I BSR 1 0 1 2 -- -- 3 -- -- 0 1 0 1 2 1 -- 3 2 -- 0 33 30 1 0 1 2 1 0 3 2 1 0 -12 83 12 1 0 1 2 -- -- 3 -- -- 0 55 18 1 0 1 2 1 -- 3 2 -- 0 28 36 1 0 1 2 1 0 3 2 1 0 -15 66 15 1 0 1 2 -- -- 3 -- -- 0 44 22 22.5 45 1 0 1 2 1 -- 3 2 -- 0 1 0 1 2 1 0 3 2 1 0 Notes Burst stop to output high impedance (CAS latency = 3) I BSH (CAS latency = 2) (CAS latency = 1) Burst stop to write data ignore I BSH I BSH I BSW Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE should be kept "H" longer than l SREX from exit cycle. 40 HM5216165 Series Timing Waveforms Read Cycle t CK t CKH t CKL " , , " , ! , , , " ! ! CLK t RC VIH CKE t RCD t RAS t RP , , ,,, , , , ,, CS t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH RAS t CS t CH t CS t CH t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH t CS t CH WE t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH A11 t AS t AH t AS t AH t AS t AH A10 t AS t AH t AS t AH Address t CS t CH DQMU /DQML I/O(input) t AC t AC t AC I/O(output) t AC Bank 0 Active Bank 0 Read t LZ t OH t OH t OH t HZ Bank 0 Precharge Burst length = 4 Bank0 Access = VIH or VIL 41 HM5216165 Series Write Cycle , ! , ! , " " ! t CK t CKH t CKL CLK t RC VIH CKE t RCD t RAS t RP t CS t CH t CS t CH t CS t CH t CS t CH CS , , RAS t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH t CS t CH WE t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH A11 t AS t AH t AS t AH t AS t AH A10 t AS t AH t AS t AH Address t CS t CH DQMU /DQML t DS t DH tDS t DH t DS t DH t DS t DH I/O(input) t RWL I/O(output) Bank 0 Active Bank 0 Write Bank 0 Precharge Burst length = 4 Bank0 Access = VIH or VIL 42 HM5216165 Series Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 , A11(BS) Address valid code R: b C: b C: b' , , ,, , , , , , , ,, , , CLK CKE CS VIH RAS CAS WE DQMU /DQML I/O(output) I/O(input) b b+3 b' b'+1 b'+2 b'+3 High-Z t RP t RSA t RCD Output mask Precharge If needed Mode Bank 1 register Active Set Bank 1 Read tRCD = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL 43 HM5216165 Series Read Cycle/Write Cycle 0 1 2 , ,, , , , , , , , , , 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE VIH RAS CAS WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) CKE CS R:a C:a R:b C:b C:b' C:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' Bank 1 Read Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Bank 1 Bank 0 Read Precharge Bank 1 Read Bank 1 Precharge VIH RAS CAS Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) R:a C:a R:b C:b C:b' C:b" High-Z a a+1 a+2 a+3 Bank 1 Active b b+1 b+2 b+3 b' Bank 0 Precharge b'+1 b" b"+1 b"+2 b"+3 Bank 0 Active Bank 0 Write Bank 1 Write Bank 1 Write Bank 1 Write Bank 1 Precharge 44 HM5216165 Series Read/Single Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 , a b c a a+1 a+3 Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge ,,, , , , , , , , , , , , CLK CS CKE VIH RAS CAS WE A11(BS) Address DQMU /DQML I/O (input) I/O (output) CKE CS R:a C:a R:b C:a' C:a a a a+1 a+2 a+3 a a+1 a+2 a+3 Bank 0 Precharge Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Bank 0 Write Read Bank 1 Precharge VIH RAS CAS WE A11(BS) Address DQMU /DQML I/O (input) I/O (output) R:a C:a R:b C:a C:b C:c Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL 45 HM5216165 Series Read/Burst Write Cycle 0 CLK CKE CS RAS CAS WE A11(BS) Address DQMU /DQML I/Q (input) I/Q (output) CKE CS RAS CAS WE A11(BS) Address DQMU /DQML I/Q (input) I/Q (output) R:a C:a R:b C:a R:a C:a R:b C:a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 a+2 a+3 a a+1 a+2 Bank 0 Active Bank 0 Read Bank 1 Active Clock Suspend a+3 Bank 0 Write Bank 0 Precharge Bank 1 Precharge VIH a a+1 a+2 a+3 a a+1 Bank 0 Active Bank 0 Read Bank 1 Active a+3 Bank 0 Write Bank 0 Precharge Read/Burst write RAS-CAS delay = 3 CAS Latency = 4 Burst Length = 4 = VIH or VIL 46 HM5216165 Series Full Page Read/Write Cycle 0 1 2 3 0 . * " & . 0- , & " ' * . 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CLK CS CKE VIH RAS CAS Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) CKE CS R:a C:a R:b a a+1 a+2 a+3 a-2 a-1 a a+1 a+2 a+3 a+4 a+5 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Burst stop Bank 1 Precharge VIH RAS CAS Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) R:a C:a R:b High-Z a a+1 a+2 a+3 a+4 a+5 a+6 a+1 a+2 a+3 a+4 a+5 Bank 0 Active Bank 0 Write Bank 1 Active Burst stop Bank 1 Precharge 47 HM5216165 Series Auto Refresh Cycle Self Refresh Cycle CLK ISREX CKE CS CKE Low CKE High , ,,, , ,, , ,, , ,, , , , , ,,, ,, , , , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH CS RAS CAS WE A11(BS) Address A10=1 R:a C:a DQMU /DQML I/O(input) I/O(output) High-Z a a+1 t RP t RC tRC Precharge If needed Auto Refresh Auto Refresh Active Bank 0 Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL RAS CAS WE A11(BS) Address DQMU /DQML I/O(imput) I/O(output) A10=1 High-Z tRP Precharge command If needed Self refresh entry command Self refresh exit ignore command or No operation Next Self refresh entry clock command enable tRC Next Auto clock refresh enable Self refresh cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 =VIH or VIL 48 HM5216165 Series Clock Suspend Mode t CESP t CEH t CES ,, ,, , , , , , , , , ,,, ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE RAS CAS Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) CKE CS R:a C:a R:b C:b a a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start Read suspend end , Bank1 Read Bank0 Precharge Earliest Bank1 Precharge RAS CAS Write cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) R:a C:a R:b C:b High-Z a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Active Active clock suspend start Active clock Bank0 Bank1 supend end Write Active Write suspend start Write suspend end Bank1 Bank0 Write Precharge Earliest Bank1 Precharge 49 HM5216165 Series Power Down Mode Precharge command If needed Power down entry Power down mode exit Active Bank 0 , , , , ,, , , ,,, ,, , , , , , CLK CKE CS CKE Low RAS CAS WE A11(BS) Address A10=1 R: a DQMU /DQML I/O(input) I/O(output) High-Z tRP Power down cycle RAS-CAS delay=3 CAS latency=2 Burst length=4 = VIH or VIL Power Up Sequence 0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55 CLK CKE VIH CS RAS CAS WE Address DQMU /DQML I/O Valld code Valld VIH High-Z tRP All banks Auto Refresh Precharge tRC Auto Refresh tRC tRSA Mode register Bank active Set If needed 50 HM5216165 Series Package Dimensions HM5216165TT Series (TTP-50D) Unit: mm 20.95 21.35 Max 50 26 1 0.27 0.07 0.25 0.05 1.15 Max 0.80 0.13 M 25 0.80 10.16 11.76 0.20 0.50 0.10 0.68 0 - 5 0.145 0.05 0.125 0.04 1.20 Max 0.13 0.05 0.10 Hitachi Code JEDEC Code EIAJ Code Weight TTP-50D -- -- 0.50 g 51 HM5216165 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 52 HM5216165 Series Revision Record Rev. 0.0 0.1 Date Jul. 29, 1994 Contents of Modification Initial issue Drawn by S. Ishikawa S. Ishikawa Approved by T. Kizaki T. Kizaki Oct. 20, 1995 Change of Command Truth Table Change of Function Truth Table Change of Simplified State Diagram Change of figures for Operation of HM5216165 Series Addit ion of f igures for READ t o WRI TE command i terval (2) n Change of description for Power-up sequence DC Characteristics: Addition of notes7 AC Characteristics tAC max (CL = 1): 28/32/36 ns to 27/32/36 ns tAC max (CL = 2): 13/15/17 ns to 12/15/17 ns tHZ min: 3/3/3 ns to 2/2/2 ns tCESP min: 5/5/5 ns to 2/3/3 ns tRWL min: 20/24/30 ns to 15/18/22.5 ns Addition of notes3 Test Conditions output load: 500 to 50 Relationship Between Frequency and Minimum Latency tRWL: 2/2/1/2/2/1/2/2/1 to 2/1/1/2/1/1/2/1/1 Addition of l SREX : 2/2/2/2/2/2/2/2/2 lAPW: 5/4/2/5/4/2/5/4/2 to 5/3/2/5/3/2/5/3/2 Change of notes2 Timing Waveforms Change of Self refresh cycle and Power up sequence Jan. 26, 1996 Change of figure for Read with auto-precharge AC Characteristics tHZ min: 2/2/2 ns to --/--/-- ns tRAS max: 10000/10000/10000 ns to 120000/120000/120000 ns tRAS max: 80000/80000/80000 ns to 120000/120000/120000 ns Dec. 20, 1996 Correct errors Addition of HM5216165-10H Series Change of description for Self-refresh Capacitance C|1, C|2: -- typ to 2 min CO: -- typ to 4 min AC Characteristics Addition of tAC (CL = 2) (HM5216165-10H) max: 9.0/12/17 ns tAC (CL = 2) max: 12/15/17 ns to 9.5/12/17 ns tAC (CL = 3) max: 8/10/12 ns to 7.5/9/12 ns tHZ min: 2/2/2 ns to --/--/-- ns Change of symbol: t RWL to tDPL Relationship Between Frequency and Minimum Latency Change of notes2 Timing Waveforms Change of Self refresh cycle 0.2 S. Ishikawa T. Kizaki 1.0 53 |
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